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> Xilinx XC9572XL cpld development board + jtag+ examples
Xilinx XC9572XL cpld development board + jtag+ examples
Development board with Xilinx XC9572XL-7C high performance CPLD
with many fully tested programs in VHDL
Datasheet available from Xilinx : XC9572XL 3.3V High-Performance CPLD (PDF)
* 2 x connectors 2x20 one with all the CPLD signals and one for user signal
* 1 x USB connector (the type found on Olympus cameras) ( it is not mounted on this version of the board since it can not be used to power 9572XL since the chip is 3.3 V)
* 2 x LEDs (one Green, One Red)
* 1 x 6 pin JTAG connector for programming/erasing the device
* Space for a 14 pin DIL package crystal oscilator on the back of the PCB
* Space for 1 14 pin SMD IC and resistors and other components on the back of the PCB
* Location in the back side of the board for your own components
The winner will receive the following in electronic format:
* Schematic of the board in PDF
* CPLD pin configuration in a text file to be used by your own projects
* How to use the CPLDs internal delay as a source for a clock
* How to connect a 7-segment displaywith VHDL code and simple schematic
* How to make a 8 bits D/A converter in VHDL with only one Resistor and one Capacitor (the cheapest possible D/A converter).
* How to make a delta sigma A/D converter in VHDL using only an external comparator
* How to use this board as XIlinx JTAG Parallel Cable IV
* How to use this board as Altera JTAG Parallel Cable
All project will work on Xilinx webpack or ISE.
* A free, downloadable PLD design environment for both Microsoft Windows and Linux!
* The industry's fastest timing closure with Xilinx SmartCompile technology
* Complete, front-to-back design environment , including the Xilinx CORE Generator system and the full PlanAhead design and analysis tool
* Integrated HDL verification with the Lite version of the ISE Simulator (ISim) as well as the Starter version of ModelSim Xilinx Edition-III (MXE-III)
* The easiest, lowest cost way to get started with the industry leader for productivity, performance, and power
You can also use Aldec's Active HDL student version to design/compile/synthesize and download your code.
* 7.5 ns pin-to-pin logic delays on all pins
* 72 macrocells with 1600 usable gates
* 3.3V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and temperature range
* Enhanced pin-locking architecture
* Flexible 36V18 Function Block
- Global and product term clocks, output enables, set and reset signals
* Extensive IEEE Std 1149.1 boundary-scan (JTAG) support
* Programmable power reduction mode in each macrocell
* Slew rate control on individual outputs
* User programmable ground pin capability
* Extended pattern security features for design protection
* 2.5V, 3.3V or 5V I/O capability
* Advanced CMOS 3.3V FastFLASH technology
