Machine Parts For Reuse Newsgroup Discussion Forum > Medium Size Parts
> New
> Electronic
> St. Louis
> 5PCS ADS7843 e 4-wire touch screen interface controller
5PCS ADS7843 e 4-wire touch screen interface controller
ADS7843 E TOUCH SCREEN CONTROLLER 4-WIRE TOUCH SCREEN INTERFACE
http://pdf.dzsc.com/20090227/200902050443212123.pdf
l 4-WIRE TOUCH SCREEN INTERFACE
l UP TO 125kHz CONVERSION RATE
l PROGRAMMABLE 8- OR 12-BIT RESOLUTION
The ADS7843 is a 12-bit sampling analog-to-digital
converter (ADC) with a synchronous serial interface
and low on-resistance switches for driving touch
screens. Typical power dissipation is 750mW at a
125kHz throughput rate and a +2.7V supply. The
reference voltage (VREF) can be varied between 1V and
+VCC, providing a corresponding input voltage range
of 0V to VREF. The device includes a shutdown mode
which reduces typical power dissipation to under
0.5mW. The ADS7843 is guaranteed down to 2.7V
Low power, high speed, and on-board switches make
the ADS7843 ideal for battery operated systems such
as personal digital assistants with resistive touch screens
and other portable equipment. The ADS7843 is available
in a 16-lead SSOP package and is guaranteed
over the 40 C to +85 C temperature range.
c1997 Burr-Brown Corporation PDS-1441C Printed in U.S.A. June, 1998
PARAMETER CONDITIONS MIN TYP MAX UNITS
Full-Scale Input Span Positive Input - Negative Input 0 VREF V
Absolute Input Range Positive Input 0.2 +VCC +0.2 V
Integral Linearity Error 2 LSB(1)
Offset Error Match 0.1 1.0 LSB
Multiplexer Settling Time 500 ns
Channel-to-Channel Isolation VIN = 2.5Vp-p at 50kHz 100 dB
Resistance CS = GND or +VCC 5 GW
VIH | IIH | +5mA +VCC 0.7 +VCC +0.3
VIL | IIL | +5mA 0.3 +0.8 V
VOL TA = 0 C to +85 C, 100kW Pull-Up 0.8 V
+VCC Specified Performance 2.7 3.6 V
Power Dissipation +VCC = +2.7V 1.8 mW
Specified Performance 40 +85 C
At TA = 40 C to +85 C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, fCLK = 16 fSAMPLE = 2MHz, 12-bit mode,
and digital inputs = GND or +VCC, unless
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for
inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user s
own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any
third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610mV.
1 +VCC Power Supply, 2.7V to 5V.
2 X+ X+ Position Input. ADC input Channel 1.
3 Y+ Y+ Position Input. ADC input Channel 2.
7 IN3 Auxiliary Input 1. ADC input Channel 3.
8 IN4 Auxiliary Input 2. ADC input Channel 4.
9 VREF Voltage Reference Input
10 +VCC Power Supply, 2.7V to 5V.
11 PENIRQ Pen Interrupt. Open anode output (requires 10kW
to 100kW pull-up resistor externally).
12 DOUT Serial Data Output. Data is shifted on the falling
edge of DCLK. This output is high impedance
13 BUSY Busy Output. This output is high impedance when
14 DIN Serial Data Input. If CS is LOW, data is latched on
15 CS Chip Select Input. Controls conversion timing and
enables the serial input/output register.
16 DCLK External Clock Input. This clock runs the SAR conversion
process and synchronizes serial data I/O.
+VCC to GND ........................................................................ 0.3V to +6V
Analog Inputs to GND ............................................ 0.3V to +VCC + 0.3V
Digital Inputs to GND ............................................. 0.3V to +VCC + 0.3V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150 C
Operating Temperature Range ........................................ 40 C to +85 C
Storage Temperature Range ......................................... 65 C to +150 C
Lead Temperature (soldering, 10s) ............................................... +300 C
NOTE: (1) Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifications.
INTEGRAL PACKAGE SPECIFICATION
LINEARITY DRAWING TEMPERATURE ORDERING TRANSPORT
PRODUCT ERROR (LSB) PACKAGE NUMBER(1) RANGE NUMBER(2) MEDIA
ADS7843E 2 16-Lead SSOP 322 40 C to +85 C ADS7843E Rails
" " " " " ADS7843E/2K5 Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC
Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering
2500 pieces of ADS7843E/2K5 will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC
At TA = +25 C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 fSAMPLE = 2MHz, unless otherwise
CHANGE IN OFFSET vs TEMPERATURE
TYPICAL PERFORMANCE CURVES (CONT)
REFERENCE CURRENT vs SAMPLE RATE
REFERENCE CURRENT vs TEMPERATURE
(X+, Y+: +VCC to Pin; X , Y : Pin to GND)
SWITCH ON RESISTANCE vs TEMPERATURE
20 40 60 80 100 120 140 160 180 200
The ADS7843 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
The basic operation of the ADS7843 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 1V and +VCC.
The value of the reference voltage directly sets the input
range of the converter. The average reference input current
depends on the conversion rate of the ADS7843.
The analog input to the converter is provided via a fourchannel
multiplexer. A unique configuration of low onresistance
switches allows an unselected ADC input channel
to provide power and an accompanying pin to provide ground
for an external device. By maintaining a differenital input to
the converter and a differential reference architecture, it is
possible to negate the switch s on-resistance error (should
this be a source of error for the particular measurement).
Figure 2 shows a block diagram of the input multiplexer on
the ADS7843, the differential input of the A/D converter, and
the converter s differential reference. Table I and Table II
control bits and the configuration of the ADS7843. The
control bits are provided serially via the DIN pin see the
Digital Interface section of this data sheet for more details.
When the converter enters the hold mode, the voltage difference
between the +IN and IN inputs (see Figure 2) is
captured on the internal capacitor array. The input current on
the analog inputs depends on the conversion rate of the
device. During the sample period, the source must charge the
internal sampling capacitor (typically 25pF). After the capacitor
has been fully charged, there is no further input
current. The rate of charge transfer from the analog source to
the converter is a function of conversion rate.
A2 A1 A0 X+ Y+ IN3 IN4 IN(1) X SWITCHES Y SWITCHES +REF(1) REF(1)
0 0 1 +IN GND OFF ON +VREF GND
1 0 1 +IN GND ON OFF +VREF GND
0 1 0 +IN GND OFF OFF +VREF GND
1 1 0 +IN GND OFF OFF +VREF GND
TABLE I. Input Configuration, Single-Ended Reference Mode (SER/DFR HIGH).
NOTE: (1) Internal node, for clarification only not directly accessible by the user.
TABLE II. Input Configuration, Differential Reference Mode (SER/DFR LOW).
FIGURE 1. Basic Operation of the ADS7843.
FIGURE 2. Simplified Diagram of Analog Input.
The voltage difference between +REF and REF (see Figure
2) sets the analog input range. The ADS7843 will operate
with a reference in the range of 1V to +VCC. There are several
critical items concerning the reference input and its wide
voltage range. As the reference voltage is reduced, the analog
voltage weight of each digital output code is also reduced.
This is often referred to as the LSB (least significant bit) size
and is equal to the reference voltage divided by 4096. Any
offset or gain error inherent in the A/D converter will appear
reduced. For example, if the offset of a given converter is 2
LSBs with a 2.5V reference, it will typically be 5 LSBs with
a 1V reference. In each case, the actual offset of the device
is the same, 1.22mV. With a lower reference voltage, more
care must be taken to provide a clean layout including
adequate bypassing, a clean (low noise, low ripple) power
supply, a low-noise reference, and a low-noise input signal.
The voltage into the VREF input is not buffered and directly
drives the capacitor digital-to-analog converter (CDAC) portion
of the ADS7843. Typically, the input current is 13mA
with VREF = 2.7V and fSAMPLE = 125kHz. This value will vary
by a few microamps depending on the result of the conversion.
The reference current diminishes directly with both
conversion rate and reference voltage. As the current from the
reference is drawn on each bit decision, clocking the converter
more quickly during a given conversion period will not
reduce overall current drain from the reference.
There is also a critical item regarding the reference when
making measurements where the switch drivers are on. For
this discussion, it s useful to consider the basic operation of
the ADS7843 as shown in Figure 1. This particular application
shows the device being used to digitize a resistive
touch screen. A measurement of the current Y position of
the pointing device is made by connecting the X+ input to
the A/D converter, turning on the Y+ and Y drivers, and
digitizing the voltage on X+ (see Figure 3 for a block
diagram). For this measurement, the resistance in the X+
lead does not affect the conversion (it does affect the
settling time, but the resistance is usually small enough that
FIGURE 3. Simplified Diagram of Single-Ended Reference
(SER/DFR HIGH, Y Switches Enabled, X+ is
However, since the resistance between Y+ and Y is fairly
low, the on-resistance of the Y drivers does make a small
difference. Under the situation outlined so far, it would not
be possible to achieve a zero volt input or a full-scale input
regardless of where the pointing device is on the touch
screen because some voltage is lost across the internal
switches. In addition, the internal switch resistance is unlikely
to track the resistance of the touch screen, providing
an additional source of error.
This situation can be remedied as shown in Figure 4. By
setting the SER/DFR bit LOW, the +REF and REF inputs
are connected directly to Y+ and Y . This makes the analogto-
digital conversion ratiometric. The result of the conversion
is always a percentage of the external resistance, regardless
of how it changes in relation to the on-resistance of
the internal switches. Note that there is an important consideration
regarding power dissipation when using the
ratiometric mode of operation, see the Power Dissipation
complete conversion can be accomplished with three serial
communications, for a total of 24 clock cycles on the DCLK
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer, switches, and reference inputs appropriately,
the converter enters the acquisition (sample) mode and, if
needed, the internal switches are turned on. After three more
clock cycles, the control byte is complete and the converter
enters the conversion mode. At this point, the input sample/
hold goes into the hold mode and the internal switches may
turn off. The next twelve clock cycles accomplish the actual
analog-to-digital conversion. If the conversion is ratiometric
(SER/DFR LOW), the internal switches are on during the
conversion. A thirteenth clock cycle is needed for the last bit
of the conversion result. Three more clock cycles are needed
to complete the last byte (DOUT will be LOW). These will
Also shown in Figure 5 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the S bit,
must always be HIGH and indicates the start of the control
byte. The ADS7843 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2). The MODE bit determines
the number of bits for each conversion, either 12 bits (LOW)
The SER/DFR bit controls the reference mode: either singleended
(HIGH) or differential (LOW). (The differential mode
is also referred to as the ratiometric conversion mode.) In
FIGURE 4. Simplified Diagram of Differential Reference
(SER/DFR LOW, Y Switches Enabled, X+ is
As a final note about the differential reference mode, it must
be used with +VCC as the source of the +REF voltage and
cannot be used with VREF. It is possible to use a high
precision reference on VREF and single-ended reference
mode for measurements which do not need to be ratiometric.
Or, in some cases, it could be possible to power the converter
directly from a precision reference. Most references
can provide enough power for the ADS7843, but they might
not be able to supply enough current for the external load
(such as a resistive touch screen).
Figure 5 shows the typical operation of the ADS7843 s digital
interface. This diagram assumes that the source of the digital
signals is a microcontroller or digital signal processor with a
basic serial interface. Each communication between the processor
and the converter consists of eight clock cycles. One
7 S Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte can start every 15th clock
cycle in 12-bit conversion mode or every 11th clock
cycle in 8-bit conversion mode.
6 - 4 A2 - A0 Channel Select Bits. Along with the SER/DFR bit,
these bits control the setting of the multiplexer input,
switches, and reference inputs, as detailed in Tables
3 MODE 12-Bit/8-Bit Conversion Select Bit.This bit controls
the number of bits for the following conversion: 12-
2 SER/DFR Single-Ended/Differential Reference Select Bit. Along
with bits A2 - A0, this bit controls the setting of the
multiplexer input, switches, and reference inputs, as
1 - 0 PD1 - PD0 Power-Down Mode Select Bits. See Table V for
TABLE IV. Descriptions of the Control Bits within the
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
S A2 A1 A0 MODE SER/DFR PD1 PD0
TABLE III. Order of the Control Bits in the Control Byte.
10 9 8 7 6 5 4 3 2 1 0 11 10 9
single-ended mode, the converter s reference voltage is
always the difference between the VREF and GND pins. In
differential mode, the reference voltage is the difference
between the currently enabled switches. See Tables I and II
and Figures 2 through 4 for more information. The last two
bits (PD1 - PD0) select the power- down mode as shown in
Table V. If both inputs are HIGH, the device is always
powered up. If both inputs are LOW, the device enters a
power-down mode between conversions. When a new conversion
is initiated, the device will resume normal operation
instantly no delay is needed to allow the device to power
up and the very first conversion will be valid. There are two
power-down modes: one where PENIRQ is disabled and
0 0 Enabled Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power.
There is no need for additional delays to assure
full operation and the very first conversion is
valid. The Y switch is on while in power-down.
0 1 Disabled Same as mode 00, except PENIRQ is disabled.
The Y switch is off while in power-down mode.
1 0 Disabled Reserved for future use.
1 1 Disabled No power-down between conversions, device is
FIGURE 5. Conversion Timing, 24-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated
10 9 8 7 6 5 4 3 2 1 0 Zero Filled...
NOTES: (1) Y Drivers are on when X+ is selected input channel (A2 - A0 = 001B), X Drivers are on when Y+ is
input channel (A2 - A0 = 101B). Y will turn on when power-down mode is entered and PD1, PD0 = 00B. (2) Drivers
remain on if power-down mode is 11B (no power-down) until selected input channel, reference mode, or power-down
TABLE V. Power-Down Selection.
FIGURE 6. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated
The control bits for conversion n+1 can be overlapped with
conversion n to allow for a conversion every 16 clock
cycles, as shown in Figure 6. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor
and the converter. This is possible provided that each
conversion completes within 1.6ms of starting. Otherwise,
the signal that has been captured on the input sample/hold
may droop enough to affect the conversion result. Note that
the ADS7843 is fully powered while other serial communications
are taking place during a conversion.
Figure 7 and Table VI provide detailed timing for the digital
Figure 8 provides the fastest way to clock the ADS7843.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively increases
the maximum conversion rate of the converter beyond
the values given in the specification tables, which
assume 16 clock cycles per conversion.
SYMBOL DESCRIPTION MIN TYP MAX UNITS
tDS DIN Valid Prior to DCLK Rising 100 ns
tDH DIN Hold After DCLK HIGH 10 ns
tDO DCLK Falling to DOUT Valid 200 ns
tDV CS Falling to DOUT Enabled 200 ns
tTR CS Rising to DOUT Disabled 200 ns
tCSS CS Falling to First DCLK Rising 100 ns
tCSH CS Rising to DCLK Ignored 0 ns
tBD DCLK Falling to BUSY Rising 200 ns
tBDV CS Falling to BUSY Enabled 200 ns
tBTR CS Rising to BUSY Disabled 200 ns
TABLE VI. Timing Specifications (+VCC = +2.7V and
Above, TA = 40 C to +85 C, CLOAD = 50pF).
FIGURE 7. Detailed Timing Diagram.
FIGURE 8. Maximum Conversion Rate, 15-Clocks per Conversion.
10 9 8 7 6 5 4 3 2 1 0 11 10 9 8 7 6 5 4 3 2
The ADS7843 output data is in Straight Binary format as
shown in Figure 9. This figure shows the ideal output code
for the given input voltage and does not include the effects
FIGURE 9. Ideal Input Voltages and Output Codes.
The ADS7843 provides an 8-bit conversion mode that can
be used when faster throughput is needed and the digital
result is not as critical. By switching to the 8-bit mode, a
conversion is complete four clock cycles earlier. This could
be used in conjunction with serial interfaces that provide 12-
bit transfers or two conversions could be accomplished with
three 8-bit transfers. Not only does this shorten each conversion
by four bits (25% faster throughput), but each conversion
can actually occur at a faster clock rate. This is because
the internal settling time of the ADS7843 is not as critical
settling to better than 8 bits is all that is needed. The clock
rate can be as much as 50% faster. The faster clock rate and
fewer clock cycles combine to provide a 2x increase in
There are two major power modes for the ADS7843: full power
(PD1 - PD0 = 11B) and auto power-down (PD1 - PD0 = 00B).
When operating at full speed and 16-clocks per conversion (as
shown in Figure 6), the ADS7843 spends most of its time
acquiring or converting. There is little time for auto powerdown,
assuming that this mode is active. Therefore, the difference
between full power mode and auto power-down is negligible.
If the conversion rate is decreased by simply slowing the
frequency of the DCLK input, the two modes remain approximately
equal. However, if the DCLK frequency is kept at the
maximum rate during a conversion but conversions are simply
done less often, the difference between the two modes is
Figure 10 shows the difference between reducing the DCLK
frequency ( scaling DCLK to match the conversion rate) or
maintaining DCLK at the highest frequency and reducing
the number of conversions per second. In the later case, the
converter spends an increasing percentage of its time in
power-down mode (assuming the auto power-down mode is
Another important consideration for power dissipation is the
reference mode of the converter. In the single-ended reference
mode, the converter s internal switches are on only
when the analog input voltage is being acquired (see Figure
5). Thus, the external device, such as a resistive touch
screen, is only powered during the acquisition period. In the
differential reference mode, the external device must be
powered throughout the acquisition and conversion periods
(see Figure 5). If the conversion rate is high, this could
substantially increase power dissipation.
The following layout suggestions should provide the most
optimum performance from the ADS7843. However, many
portable applications have conflicting requirements concerning
power, cost, size, and weight. In general, most
portable devices have fairly clean power and grounds
because most of the internal components are very low
power. This situation would mean less bypassing for the
converter s power and less concern regarding grounding.
Still, each situation is unique and the following suggestions
For optimum performance, care should be taken with the
physical layout of the ADS7843 circuitry. The basic SAR
architecture is sensitive to glitches or sudden changes on the
power supply, reference, ground connections, and digital
inputs that occur just prior to latching the output of the
analog comparator. Thus, during any single conversion for
an n-bit SAR converter, there are n windows in which
FS = Full-Scale Voltage = VREF
NOTES: (1) Reference voltage at converter: +REF ( REF). See Figure 2.
(2) Input voltage at converter, after multiplexer: +IN ( IN). See Figure 2
FIGURE 10. Supply Current vs Directly Scaling the Frequency
of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
large external transient voltages can easily affect the conversion
result. Such glitches might originate from switching
power supplies, nearby digital logic, and high power devices.
The degree of error in the digital output depends on
the reference voltage, layout, and the exact timing of the
external event. The error can change if the external event
changes in time with respect to the DCLK input.
With this in mind, power to the ADS7843 should be clean
and well bypassed. A 0.1mF ceramic bypass capacitor should
be placed as close to the device as possible. A 1mF to 10mF
capacitor may also be needed if the impedance of the
connection between +VCC and the power supply is high.
The reference should be similarly bypassed with a 0.1mF
capacitor. If the reference voltage originates from an op
amp, make sure that it can drive the bypass capacitor without
oscillation. The ADS7843 draws very little current from the
reference on average, but it does place larger demands on the
reference circuitry over short periods of time (on each rising
edge of DCLK during a conversion).
The ADS7843 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high frequency
noise can be filtered out, voltage variation due to line
frequency (50Hz or 60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the analog ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry or battery connection point. The ideal layout will
include an analog ground plane dedicated to the converter
and associated analog circuitry.
In the specific case of use with a resistive touch screen, care
should be taken with the connection between the converter
and the touch screen. Since resistive touch screens have
fairly low resistance, the interconnection should be as short
and robust as possible. Longer connections will be a source
of error, much like the on-resistance of the internal switches.
Likewise, loose connections can be a source of error when
the contact resistance changes with flexing or vibrations.
